1. Field of the Invention
The present invention is related to a DC recovery circuit for correcting a shift or deviation contained in a direct current level (will be referred to as a xe2x80x9cDC levelxe2x80x9d hereinafter) of a digital signal entered by way of a capacitor coupling.
2. Description of the Related Art
In a serial data transmission system, a clock data recovery circuit is provided in an input stage of a data reception unit thereof in order to correctly receive serial data which is transmitted via a transmission line. This clock data recovery circuit produces a recovery clock having a constant time period in synchronism with the serial data, and again correctly sets timing of the serial data based upon this produced recovery clock to thereby output the correctly set serial data as retimed data.
For example, assuming now that in a data reception unit equipped with this clock data recovery circuit as an input stage, a power supply voltage is selected to be 3.3 V and a level PECL of an internal signal (plus power supply ECL) is selected to be 200 mVpp, the normal ECL (emitter-coupled logic) signal cannot be directly entered into this data reception unit. Therefore, in order that the serial data corresponding to the ECL signal can be entered, this serial data transmission system employs the below-mentioned arrangement.
In other words, as indicated in FIG. 1, an ECL signal outputted from an ECL circuit (IC) 101 which is operated under a minus power supply Vss (for example, xe2x88x924.5 V) is inputted via an attenuator 102 and a coupling capacitor 103 to a data reception unit (IC) 104. Furthermore, a shift (deviation) contained in the DC level is corrected by a DC recovery circuit 105 arranged at an input stage of this data reception circuit 104.
It should be noted that in the data reception circuit 104, serial data corresponding to such an ECL signal whose DC level is corrected by the DC recovery circuit 105 is supplied to both a PLL (phase-locked loop) circuit 106 and a re-timing circuit 107. Both this PLL circuit 106 and the re-timing circuit 107 will constitute the clock data recovery circuit. Then, the recovery clock is produced by the PLL circuit 106, and the timing of the received serial data is again set by the re-timing circuit 107 based upon the recovery clock so as to be outputted as retimed data.
On the other hand, when a digital signal is entered by way of a capacitor coupling manner, as indicated in FIG. 2A, an amplitude center level of the digital signal would be shifted with respect to a DC center level (bias level), as represented in FIG. 2B, depending upon the mark ratio of the data corresponding to a ratio of High (logic signal 1) to Low (logic signal 0). To correct the shift of the DC level of this signal (b), as shown in FIG. 3, a quantizing feedback circuit is employed. This quantizing feedback circuit is arranged by an input circuit 111; an adder 112 for entering the output of this input circuit 111 as one input thereof; a comparator 113 for judging a logic state of an added output from this adder 112, namely for judging High/Low; and a low-pass filter 114 for feeding a DC component of the output from this comparator 113 back to the adder 112 as another input thereof.
This quantizing feedback circuit may correct the shift contained in the DC level of the input signal in such a manner that a DC component of an output signal is extracted from an amplitude of this output signal by the low-pass filter 114, and this extracted DC component is fed back to the adder 112 as another input thereof in order to be added to the input signal. To correctly operate this quantizing feedback circuit, the amplitude of the input signal for this quantizing feedback circuit is required to be equal to that of the output signal from this quantizing feedback circuit.
In FIG. 4, there is shown an arrangement of a conventional DC recovery circuit with using a quantizing feedback circuit. This DC recovery circuit is arranged by employing an input unit amplifier 121, a quantizing feedback circuit 122 for correcting a DC level of an output signal derived from this input unit amplifier 121, an AGC (automatic gain control) circuit 123 for controlling an amplitude of the output signal derived from the input unit amplifier 121, and also a reference amplifier 124 for supplying a reference signal to this AGC circuit 123.
In the DC recovery circuit with employment of the above-explained circuit arrangement, when the amplitude of the output signal of the quantizing feedback circuit 122 is set to 200 mVpp for the next-staged circuit, a signal having the same amplitude (200 mVpp) must be entered as the input signal of the quantizing feedback circuit 122. To this end, both the amplitude (200 mVpp) of the reference signal and the amplitude of the input signal of the quantizing feedback circuit 122 are detected, and then a signal used to control the amplitudes is produced in the AGC circuit 123. Based on this control signal, the amplitude of the input signal is controlled to be 200 mVpp in the input unit amplifier 121, and then the amplitude-controlled input signal is outputted.
Since the above-described conventional DC recovery circuit is arranged in such a manner that the gain of the input unit amplifier 121 is controlled by the control signal of the AGC circuit 123 so as to execute the AGC (automatic gain control) with respect to the input signal, and therefore, the amplitude of the input signal to the quantizing feedback circuit 122 is made coincident with the amplitude of the output signal thereof, it is required to employ the input unit amplifier 121 having such a wider dynamic range than that of the input signal in order to accept this input signal having the large amplitude.
However, as apparent from one example of the circuit arrangement of this input unit amplifier 121 shown in FIG. 5, both a transistor portion thereof to which an AGC input is applied and another transistor portion thereof to which a signal is inputted may constitute a so-called xe2x80x9clongitudinally stackedxe2x80x9d structure between the power supply Vcc and the ground (GND). As a result, in such a case that the voltage of this power supply Vcc is low, for instance, 3.3 V, there is a limitation to widen the dynamic range of the input unit amplifier 121. As a consequence, this input unit amplifier 121 can hardly accept such an ECL signal whose amplitude is large.
The present invention has been made to solve the above-described problems, and therefore, has an object to provide a DC recovery circuit capable of receiving an ECL signal even under low power supply voltage.
A DC recovery circuit, according to the present invention, is featured by comprising: adding means for inputting thereinto a digital signal entered via a coupling capacitor as one input of the adding means; comparing means for judging a logic state of an output signal of the adding means; extracting means for extracting a DC component of the output signal from the comparing means to enter the extracted DC component to another input of the adding means; and control means for controlling the comparing means in order that an amplitude of the output signal from the comparing means is made coincident with an amplitude of the one input signal of the adding means.
In the DC recovery circuit with the above-described circuit arrangement, the extracting means extracts the DC component of the output signal of the comparing means by processing this signal. The DC component constitutes another input of the adding means, and is added to one input of the adding means by this adding means. As a result, the DC recovery circuit corrects the shift contained in the DC level of the input signal. At this time, the control means controls the comparing means in such a manner that the amplitude of the output signal of this comparing means is made coincident with the amplitude of one input signal of the comparing means.